CMOS image sensors first came to the fore in relatively low-performance applications where shuttering was not required, scene dynamic range was low, and moderate to high noise levels could be tolerated. A CMOS sensor technology enabling a higher level of integration of an image array with associated processing circuits would be beneficial to many digital applications such as, for example, in cameras, scanners, machine vision systems, vehicle navigation systems, video telephones, computer input devices, surveillance systems, star trackers, motion detection systems, image stabilization systems and high-definition television imaging devices.
The advantages of CMOS imagers over CCD imagers are that CMOS imagers have a low voltage operation and low power consumption; CMOS imagers are compatible with integrated on-chip electronics (control logic and timing, image processing, and signal conditioning such as A/D conversion); and CMOS imagers allow random access to the image data. On-chip integration of electronics is particularly advantageous because of the potential to perform many signal conditioning functions in the digital domain (versus analog signal processing) as well as to achieve a reduction in system size and cost.
FIGS. 1A and 1B are cross-sectional views of conventional CMOS pixels known as 3T pixels (for three-transistor pixel) and 5T pixels (for 3-transistor plus 2-transfer gate pixel). More precisely, the 3T pixel 10 of FIG. 1A includes three NMOS transistors 12, 14, 16 standing for a reset transistor 12, a source follower transistor 14 and a row transistor 16. The reset transistor 12 is electrically connected to a sense node 18. The sense node 18 is formed of an n+ sense node diffusion 22 and a pinned photodiode 20. The pinned photodiode 20 includes a thin p-type pinning layer 26 overlying a custom n-diode implant 24, that in turn, overlies and forms a depletion region with a p-epitaxial layer 30. A p-substrate 32 underlies the p-epitaxial layer 30. A p-well 34 is formed adjacent the pinned photodiode 20 in the p-epitaxial layer 30 for isolating the 3T pixel 10 from neighboring pixels. A p+ return contact 36 is formed proximal to the other side of the pinned photodiode 20 and is held at ground potential (about 0V) for providing a return and ground reference for the 3T pixel. A p-well 38 is formed adjacent to the p+ return contact 36.
When operated, a RESET CLOCK (about 3.3 V) applied to the gate of the reset transistor 12 causes a reverse bias on the pinned photodiode 20. The source follower transistor 14 and the row transistor 16 are coupled between a drain supply VDD of about 3.3V and an output signal terminal COLUMN VIDEO. The drain of the reset transistor 12 is connected to VDD; the gate of the reset transistor 12 is connected to a RESET clock; and the source of the reset transistor 12 is connected to the cathode of the pinned photodiode 20 so that the reset transistor 12 operates as a switch. The source of the source follower transistor 14 is connected to the drain of the row transistor 16, and the source of the row transistor 16 is connected to output terminal COLUMN VIDEO. In applications, a plurality of such 3T pixels is coupled to the same output terminal COLUMN VIDEO. By selectively applying row address signal ROW SELECT to the gate of the selected row transistor 16, different rows may be coupled to the output terminal COLUMN VIDEO (i.e., a column bus).
The 5T pixel 40 (FIG. 1B), also known as a charge transfer pixel, is similar to the 3T pixel 10 (FIG. 1A) except that the 5T pixel 40 has a transfer gate 42 coupled between the sense node 44 and the pinned photodiode 20. The sense node 44 may be isolated from the pinned photodiode 20 by transfer gate 42. As a result, charge may be transferred from a photodetection region to the sense node 44 when a positive voltage, for example 3.3 V, is applied to the input TRANSFER GATE 1, where a resulting voltage is read out by the source follower transistor 14.
The 5T pixel 40 also includes a second transfer gate 46 abutting the side of the pinned photodiode 20 distal to the transfer gate 42. An n+ drain 48 is formed adjacent to the sense node 44 distal to the pinned photodiode 20 and is also tied to VREF (about +3.3 V). The second transfer gate 46 may be used as a global reset for the imager and as an antiblooming gate for preventing excess charge generated in the pinned photodiode 20 from “blooming” through the transfer gate 42 to the sense node 44 when a voltage is applied to the input TRANSFER GATE 2 that is more positive than the transfer gate-to-sense node voltage.
FIG. 2A is a potential diagram illustrating conventional operation of the 5T pixel 40 of FIG. 1B. FIG. 2B shows a plot of signal output (voltage) of the 5T pixel 40 of FIG. 1B during an integration time for various incoming illumination levels. Referring now to FIGS. 1B, 2A, and 2B, the p+ pinning region 26 of the photodiode 24 (hereinafter PPD 24) is generally held at ground potential and is also grounded to the substrate 32, while the n+ contact 48 (hereinafter the the anti-blooming drain 48) is formed adjacent to the second transfer gate 44 (hereinafter TRANSFER GATE 2) distal to the PPD 24 and may be tied to VREF (about +3.3 V). During an integration time, charge accumulates in the PPD 26. When TRANSFER GATE 1 is set to a logical “high” (about +3.3 V), the potential under TRANSFER GATE 1 “falls” toward VREF, and charge moves towards the sense node 44 where it is converted to a voltage and read out by a combination the reset transistor 12, the source follower transistor 14, and the row transistor 16 and external circuitry.
Referring now to FIG. 2B, if the incoming light level is relatively low, the voltage output of the 5T pixel 40 has a first slope 56 that is substantially monotonically increasing and rises to a level 58 at the end of an integration time. For the same 5T pixel 40 having a higher incoming light level, more charge accumulates in the PPD 26 and thus more charge is transferred and integrated in the same time interval. As a result, the corresponding integrated output voltages have correspondingly greater slopes 60, 64 and higher final output voltages 70, 72, respectively. Above a certain incoming light level, the pixel saturates by spilling over charge into the anti-blooming drain 48, so that the final slope of the output voltage flattens out at a saturation voltage 74 at earlier times 76, 78. Thus, dynamic range is limited.
Accordingly, what would be desirable, but has not yet been provided, is a method of operating a CMOS pixel that may operate over a larger dynamic range.